In modern integrated circuit (IC) designs, there often is a requirement to generate voltage levels above available supply voltages (VDD) or below ground. For this purpose, voltage generators are built from charge pumps. A charge pump typically precharges a capacitor to the available supply voltage VDD, then either pushes the capacitor's low potential side to VDD or its high potential plate to GND to create a boosted voltage at an output node (either 2*VDD or −VDD). In practical application, multiple charge pump cells, having a common size, usually are coupled to the output node to meet an estimated load current that will cause the boosted voltage to drain. These charge pump cells usually are controlled by a single clock source. The voltage at the output node may include a “ripple” effect as the charge pumps inject charge to the output node at the clocked rate and as load devices drain current from the output node.
In a clocked charge pump design, the voltage ripple may have a fundamental frequency based on the clock source and a magnitude proportional to:ILOAD*TCLK/CLOAD,  (Eq. 1)where ILOAD represents a drain current from the output node, CLOAD represents a capacitance of a load device and TCLK represents a period of a driving clock. In certain applications, a significant voltage ripple can cause chip malfunction or significantly reduce a circuit's performance. For high performance applications, for example, often a large decoupling capacitor must be added to an output of the charge-pump output to reduce the ripple. Sometimes, a linear low drop-out regulator is required to reduce ripple further. However, there is a cost associated with these techniques: large decoupling capacitors can consume considerable chip area and the drop out associated with a linear regulator can make it unsuitable for certain low voltage applications. Another way to reduce ripple would be to reduce clock period, but there are many other constraints on choosing clock frequency which makes this method less practical.
U.S. patent application Ser. No. 13/214,904, assigned to the assignee of the present invention, the disclosure of which is incorporated herein, describes a scheme which multiple clock stages of a ring oscillator or delay line drive respective charge pumps. Transitions of each charge pump are offset from the others due to the delays associated with each element in the delay line. Therefore, for a common number N of charge pumps, the voltage drop rate can be reduced by N/2. Another benefit is that the fundamental frequency of voltage ripple is N/2 times of the clock frequency and it is limited only by the delay inherent in an inverter pair of the ring oscillator. This scheme yields significant improvement on ripple reduction compared to a single clock phase driving scheme. However, the design is limited by the unit delay in the delay chain and may not be sufficient for some applications.
Accordingly, the inventors perceive a need in the art that further reduces the effects of ripples in multi-stage charge pump voltage generators.